Cypress Semiconductor /psoc63 /PERI /DIV_CMD

(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed.

If DIV_SEL is ‘63’ and TYPE_SEL is ‘3’ (default/reset value), no divider is specified and no clock signal(s) are generated.

Specifies the divider type of the divider on which the command is performed: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.

(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times.

If PA_DIV_SEL is ‘63’ and PA_TYPE_SEL is ‘3’, ‘clk_peri’ is used as reference.

Specifies the divider type of the divider to which phase alignment is performed for the clock enable command: 0: 8.0 (integer) clock dividers. 1: 16.0 (integer) clock dividers. 2: 16.5 (fractional) clock dividers. 3: 24.5 (fractional) clock dividers.

Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to ‘1’ and HW sets this field to ‘0’.

The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled.

The HW sets the DISABLE field to ‘0’ immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to ‘0’ immediately.

Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to ‘1’ to enable a divider and HW sets this field to ‘0’ to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to ‘0’. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps: 0: Disable the divider using the DIV_CMD.DISABLE field. 1: Configure the divider’s DIV_XXX_CTL register. 2: Enable the divider using the DIV_CMD_ENABLE field.

The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either ‘clk_peri’ (typical usage) or to ANY enabled divider.

The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider.

The HW sets the ENABLE field to ‘0’ when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to ‘1’ when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of ‘clk_peri’/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to ‘clk_peri’ takes affect immediately. SW can set this field to ‘0’ during phase alignment to abort the enabling process.